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USBUFxxW6
A. S. D. EMI filter and line termination for USB upstream ports
Application
EMI Filter and line termination for USB upstream ports on:

USB Hubs PC peripherals SOTT323-6L
Features

Monolithic device with recommended line termination for USB upstream ports Integrated Rt series termination and Ct bypassing capacitors. Integrated ESD protection Small package size
Table 1.
Order Codes
Marking UU1 UU2
Part Number USBUF01W6 USBUF02W6
Description
The USB specification requires upstream ports to be terminated with pull-up resistors from the D+ and D- lines to Vbus. On the implementation of USB systems, the radiated and conducted EMI should be kept within the required levels as stated by the FCC regulations. In addition to the requirements of termination and EMC compatibility, the computing devices are required to be tested for ESD susceptibility. The USBUFxxW6 provides the recommended line termination while implementing a low pass filter to limit EMI levels and providing ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device is packaged in a SOT323-6L which is the smallest available lead frame package (50% smaller than the standard SOT23).
Figure 1.
Functional diagram
3.3 V Rt Rp D4 Ct
D1
Grd
3.3 V
Rt D2 Ct D3
Rt CODE 01 CODE 02 33 22 10%
Rp 1.5 k 1.5 k 10%
Ct 47 pF 47 pF 20%
Benefits

Tolerance
EMI / RFI noise suppression Required line termination for USB upstream ports ESD protection exceeding IEC 61000-4-2 level 4 High flexibility in the design of high density boards Tailored to meet USB 1.1 standard
Complies with the following standards:
IEC 61000-4-2, level 4 15 kV (air discharge) 8 kV (contact discharge)
MIL STD 883E, Method 3015-7 Class 3 C = 100 pF R = 1500 3 positive strikes and 3 negative strikes (F = 1 Hz)
February 2006
Rev 5
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www.st.com 11
Characteristics
USBUFxxW6
1
Characteristics
Table 2.
Symbol
Absolute ratings (Tamb = 25 C)
Parameter ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge ESD discharge - MIL STD 883E - Method 3015-7 Maximum junction temperature Storage temperature range Lead solder temperature (10 second duration) Operating temperature range Power rating per resistor Value 16 9 25 150 - 55 to + 150 260 -40 to 70 100 Unit
VPP
kV C C C C mW
Tj Tstg TL Top
P
2
Technical information
Figure 2. USB standard requirements
3.3V 1.5k
Rt
D+
Twisted pair shielded
D+
Rt Ct Rt
Full-speed or Low-speed USB Transceiver
Ct Rt
Full-speed USB Transceiver
DHost or Hub port
Ct 15k 15k
Zo = 90ohms 5m max
DCt
Hub 0 or Full-speed function
FULL SPEED CONNECTION
3.3V 1.5k
Rt
D+
Untwisted unshielded
D+
Rt Ct Rt
Full-speed or Low-speed USB Transceiver
Ct Rt
Low-speed USB Transceiver
DHost or Hub port
Ct 15k 15k
3m max
DCt
Hub 0 or Low-speed function
LOW SPEED CONNECTION
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USBUFxxW6
Technical information
2.1
Application example
Figure 3.
Downstream port
Host/Hub USB por transceivert
Implementation of ST solutions for USB ports
USBDF01W5
Rt D+ in Ct Rd D+ out
USBUF01W6
D2 Gnd D1
Upstream port
D+
Peripheral transceiver
D+
D+
CABLE
D+
Ct Rt Ct Rt 3.3 V Rp
Gnd
Gnd Ct Rd D- in Rt D- out
D-
D-
DD3
3.3V
D4
D-
FULL SPEED CONNECTION
Downstream port
Host/Hub USB por transceivert
USBDF01W5
Rt D+ in Ct Rd D+ out
USBUF01W6
D2 Gnd D1
Upstream port
D+
Peripheral transceiver
D+
D+
CABLE
D+
Ct Rt Ct Rt 3.3 V Rp
Gnd
Gnd Ct Rd D- in Rt D- out
D-
D-
DD3
3.3V
D4
D-
LOW SPEED CONNECTION
2.2
EMI filtering
Current FCC regulations requires that class B computing devices meet specified maximum levels for both radiated and conducted EMI.

Radiated EMI covers the frequency range from 30 MHz to 1 GHz. Conducted EMI covers the 450 kHz to 30 MHz range.
For the types of devices utilizing the USB, the most difficult test to pass is usually the radiated EMI test. For this reason the USBUFxxW6 device is aiming to minimize radiated EMI. The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted EMI because the magnetic field of both conductors cancels each other. The inside of the PC environment is very noisy and designers must minimize noise coupling from the different sources. D+ and D-must not be routed near high speed lines (clocks spikes). Induced common mode noise can be minimized by running pairs of USB signals parallel to each other and running grounded guard trace on each side of the signal pair from the USB controller to the USBUF device. If possible, locate the USBUF device physically near the
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Technical information
USBUFxxW6
USB connectors. Distance between the USB controller and the USB connector must be minimized. The 47 pF (Ct) capacitors are used to bypass high frequency energy to ground and for edge control, and are placed between the driver chip and the series termination resistors (Rt). Both Ct and Rt should be placed as close to the driver chip as is practicable. The USBUFxxW6 ensures a filtering protection against ElectroMagnetic and RadioFrequency Interferences thanks to its low-pass filter structure. This filter is characterized by the following parameters:

cut-off frequency Insertion loss high frequency rejection. USBUFxxW6 typical attenuation Figure 5. Measurement configuration
Figure 4.
S21 (dB) 0
-10
50
TEST BOARD
UUx
-20
Vg
50
-30 1 10 100 Frequency (MHz) 1,000
2.3
ESD PROTECTION
In addition to the requirements of termination and EMC compatibility, computing devices are required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe. This test requires that a device tolerates ESD events and remains operational without user intervention. The USBUFxxW6 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at: Vcl = VBR + Rd . IPP This protection function is splitted in 2 stages. As shown in figure 6, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor Rt. Such a configuration makes the output voltage very low at the output.
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USBUFxxW6 Figure 6. USBUFxxW6 ESD clamping behavior
Rg
Technical information
S1
Rt
S2
Rd
VPP
Vinput Voutput
Rd
Rload
VBR
VBR
Device to be protected
ESD Surge
USBUF01W6
Figure 7.
ESD SURGE
Measurement board
TEST BOARD
16kV Air Discharge
UUx
Vin
Vout
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamical resistance value Rd. By taking into account these following hypothesis: Rt > Rd, Rg > Rd and Rload > Rd, it gives these formulas:
R g V BR + R d V g Vinput = ---------------------------------------------Rg R t V BR + R d Vinput Vouput = -----------------------------------------------------Rt
The results of the calculation done for Vg = 8 kV, Rg = 330 (IEC 61000-4-2 standard), VBR = 7 V (typ.) and Rd = 1 (typ.) give: Vinput = 31.2 V Voutput = 7.95 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due the low current involved after the resistance Rt. The measurements done hereafter show very clearly (figure 8) the high efficiency of the ESD protection:

no influence of the parasitic inductances on Voutput stage Voutput clamping voltage very close to VBR (breakdown voltage) in the positive way and - VF (forward voltage) in the negative way
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Technical information Figure 8.
USBUFxxW6 Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge
Vin Vin
Vout
Vout
Positive surge
Negative surge
Please note that the USBUFxxW6 is not only acting for positive ESD surges but also for negative ones. For these kinds of disturbances it clamps close to ground voltage as shown in Figure 8. (negative surge.
2.4
Latch-up phenomena
The early ageing and destruction of IC's is often due to latch-up phenomenon which is mainly induced by dV/dt. Thanks to its structure, the USBUFxxW6 provides a high immunity to latch-up phenomenon by smoothing very fast edges.
2.5
Crosstalk behavior
Figure 9. Crosstalk phenomenon.
RG1 Line 1
VG1 RG2 Line 2
RL1
1 VG1 + 1 2VG2
VG2
RL2
2 VG2 + 2 1VG1
DRIVERS
RECEIVERS
The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k).
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USBUFxxW6
Technical information
Figure 10. Figure 10: Analog crosstalk measurements
Figure 11. Typical analog crosstalk results
Analog crosstalk (dB) 0
TEST BOARD
-20 -40
50
50
UUx
Vg
-60 -80 -100 1 10 100 Frequency (MHz) 1,000
Figure 10. gives the measurement circuit for the analog crosstalk application. In Figure 11., the curve shows the effect of the D+ cell on the D-cell. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -37 db. Figure 12. Digital crosstalk measurements configuration
+5V 74HC04
3.3 V
+5V 74HC04
D+
D1
Rt Ct
Rp D4
Square Pulse Generator
VG1 +5V DD2 Gnd Rt Ct D3 3.3 V
21 VG1
Figure 12. shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure 13. Digital crosstalk results
VG1
21VG1
Figure 13. shows, with a signal from 0 to 5 V and rise time of few ns, the impact on the disturbed line is less than 250 mV peak to peak. No data disturbance was noted on the other line.The measurements performed with falling edges gives an impact within the same range.
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Technical information
USBUFxxW6
2.6
Transition times
This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the signal edges are maintained within the 4 -20 ns stipulated USB specification limits. To verify this point, we have measured the rise time of VD+ voltage with and without the USBUFxxW6 device. Figure 14. Typical rise and fall times: measurement configuration Figure 15. Typical rise times with and without protection device
without
74HC04 D+
+5V
+5V
+5V
74HC04
Square Pulse Generator
USBDF 01W6
D-
with
Figure 14. shows the circuit used to perform measurements of the transition times. In Figure 15., we see the results of such measurements: trise = 3.8 ns driver alone trise = 7.8 ns with protection device The adding of the protection device causes the rise time increase of roughly 4ns. Note: Rise time has been measured between 10% and 90% of the signal (resp. 90% and 10%)
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USBUFxxW6
Packaging information
3
Packaging information
Table 3. SOT323-6L Package Mechanical Data
DIMENSIONS REF.
A E
Millimeters Min. A 0.8 0 0.8 0.15 0.1 1.8 1.15 Max. 1.1 0.1 1 0.3 0.18 2.2 1.35
Inches Min. 0.031 0 0.031 0.006 0.004 0.071 0.045 Max. 0.043 0.004 0.039 0.012 0.007 0.086 0.053
e b e
D
A1 A2 b
A1 A2
c D E e
Q1
c
0.65 Typ. 1.8 0.1 0.1 2.4 0.4 0.4
0.025 Typ. 0.071 0.004 0.004 0.094 0.016 0.016
L
HE
HE L Q1
Figure 16. Recommeneded footprint (dimensions in mm)
0.65
1.05
0.80
2.9
1.05
0.40
Table 4.
Lead plating Lead plating thickness Lead material
Mechanical specifications
Tin-lead 5 m min 25 m max Sn / Pb (70% to 90%Sn) 10 m max Molded epoxt UL94V-0
Lead coplanarity Body material Flammability
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Ordering Information
USBUFxxW6
4
Ordering Information
Ordering code USBUF01W6 USBUF02W6 Marking UU1 UU2 Package SOT323-6L SOT323-6L Weight 5.4 mg 5.4 mg Base qty 3000 3000 Delivery mode Tape & reel Tape & reel
5
Revision History
Date Mar-2002 Feb-2005 28-Feb-2006 Revision 3A 4 5 Last update. Layout update. No content change. Operating temperature range updated to -40 to 70 C. Layout updated to current standard. Description of Changes
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USBUFxxW6
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